(1) Field of the Invention
The present invention relates to a test socket and method for producing known good dies using a test socket. More particularly, it relates to a test socket and a method for producing known good dies in which known good dies can be mass-produced and carried through tests such as the electrical and burn-in tests, performed on a plurality of semiconductor chips which are separated from a wafer by conventional semiconductor manufacturing steps.
(2) Description of Related Art
Generally, various tests are carried out on a semiconductor chip in order to ensure device reliability. The tests are typically divided between electrical tests for identifying normal or abnormal operation and circuit disconnections, and a burn-in test for examining the durability of a semiconductor chip and the occurrence of flaws, performed by connecting some input/output terminals of the semiconductor chips to a test signal generating circuit and applying stresses, such as higher than normal temperature, voltage, current, etc.
For example, in case of a dynamic random access memory, a burn-in test is performed to identify any flaws in memory circuits and memory cells.
The semiconductor chip has disadvantages such as deterioration of insulating film in a gate oxide layer at the time of being used under normal conditions during burn-in. Accordingly, chips having defects are detected by the burn-in test for removing such defects, which are to be shipped, in order to ensure the reliability of the goods.
However, the electrical and burn-in test is rarely performed on normal bare chips separated from a wafer because of the difficulty in electrical connection with the test signal generating circuit. Therefore, the electrical and burn-in tests are carried out on semiconductor chips which are packaged by molding compounds, (e.g., epoxy molding compound (EMC)). Such a semiconductor package includes an untested semiconductor chip mounted on a die pad, inner leads connected to bonding pads of the chip by wires, and a package body shielding the chip and wires.
Outer leads, opposite to respective inner leads protrude from the body of the semiconductor package, and are inserted in a test socket having socket holes for receiving the outer leads. After that, the test socket is mounted on a burn-in test substrate to carry out the burn-in test.
However, such a semiconductor package has limits in high density mounting. A flip chip technique has been developed in which a plurality of bare chips are mounted directly on an insulating ceramic substrate, instead of using individual packages. In addition, various techniques for making a semiconductor chip with high speed, high capacitance and very large scale integration in a small size have been proposed. A representative technique is the multi chip module (MCM).
The MCM includes a plurality of semiconductor chips mutually connected to each other on a multi-layer ceramic substrate on which high density wiring is provided, whereby a very large scale integration is obtained. Computer companies such as IBM, DEC, Hitachi, etc. have applied the MCM to supercomputer.
The MCM, however, has technical and economical limitations, even though the MCM can mount more semiconductor chips than a conventional singular semiconductor chip packaging technique, with improved integration. Its production yield is remarkably decreased, thereby increasing the manufacturing cost. In particular, the major problem of the MCM is the difficulty of identifying known good dies, to ensure reliability as high as that of conventional packaging techniques.
Even though the demand for known good dies used in the MCM is increased, it is difficult to mass-produce known good dies at a low cost. A single bare chip separated from a wafer does not have outer leads and cannot use the above-described test socket for semiconductor package testing. Thus, electrical and burn-in tests cannot be performed before the single bare chip is mounted on a printed circuit board.
In order to solve these problems, various types of techniques have been developed, such as a hot chuck probe technique, a tape automated bonding (TAB) technique, a technique for using a flip chip test socket adapter, a wafer-level test technique, and a method for making a known good die produced by the wafer-level test technique and test housing. However, these techniques have the same problem of unduly high manufacturing cost for mass-production.
Referring first to the hot chuck probe technique, a hot chuck probe has terminals which contact the bonding pads of the chip to carry out the test. This technique does not need additional steps to process the wafer, and can supply users with bare chips. However, it requires a great deal of time to carry out the test. For different types of semiconductor chips, additional hot chuck probes are required, thereby increasing the manufacturing cost.
The TAB technique tests semiconductor chips by connecting respective ends of thin metal film leads to test terminals, wherein a semiconductor chip is connected via a chip bump to the other ends of thin metal film leads of a tape carrier in an insulating film.
A technique using the flip chip test socket adaptor is disclosed in U.S. Pat. No. 5,006,792. A bare chip having solder bumps associated with each bonding pad of the chip is inserted in an exclusive adaptor to carry out the test. The test socket adaptor is provided with a board on which cantilever beams are correspondingly connected to the solder bumps of the semiconductor chip. The board is received in a case, and input/output terminals extending outside the case are inserted in a burn-in test substrate to perform the burn-in test.
The above-mentioned techniques are widely known and can carry out testing of a bare chip prior to packaging.
However, the process for making a necessary bump on bonding pads of a single, base semiconductor chip requires expensive equipment for accommodating the minute pitch, which exists between the bonding pads as a result of high integration. Besides, the semiconductor chips must be handled individually during the tests, thereby making chip handling complicated, and decreasing the yield of the tested chips, resulting in an increase of the manufacturing cost, compared with the cost of manufacturing general semiconductor packages.
The tape carrier according to the TAB method, cannot be recycled, and the technique of using the test socket adaptor is complicated due to unique structure of the test socket, thereby making the manufacture difficult.
The wafer-level test is an ideal technique for carrying out testing collectively after all the chips formed on the wafer have been connected with contact terminals. However, it is impossible to make contact terminals corresponding to the bonding pads for all the chips, and noise may also occur due to using the same substrate.
The following description, with reference to FIG. 1, of a method for making a known good die with by a test housing is disclosed in U.S. Pat. No. 5,173,451 in order to solve the above described problems.
First, exterior connector leads 14 are installed on the exterior of a ceramic substrate 12 of rectangular shape and having a die-receiving cavity 11 at its center for mounting a semiconductor chip 16 therein by means of a piece of bonding tape 13. Contact pads 17 are formed on an end portion inside the ceramic substrate 12 corresponding to the bonding pads 15 of the semiconductor chip 16. The contact pads 17 are connected to the exterior connector leads 14 by internal wiring (not illustrated).
The bonding pads 15 and contact pads 17 are connected by a wire 18, which is soft-bonded to the pads 15, 17 to facilitate removal of the wire 18.
On an upper portion of the ceramic substrate 12, a flange 19 of rectangular shape is installed, to seal the inside thereof. The exterior connector leads 14 are then inserted in a test board (not illustrated) to carry out the burn-in test.
In producing the known good dies provided in the test housing, a single semiconductor chip 16 is mounted by means of a piece of adhesive tape 13, in the die-receiving cavity 11 of the ceramic substrate 12. The substrate 12 has exterior connector leads 14, as in the conventional semiconductor package. The bonding pads 15 of the semiconductor chip 16 are connected to the contact pads 17 inside the substrate 12 by the wire 18. A plurality of bare good dies are likewise mounted on the test board in order to permit one to carry out the burn-in test collectively on all of them.
After testing, the tested bare dies in the test housing 10 are separated from the test board, and after the flange 19 and the wires 18 are sequentially removed, the semiconductor chips 16 are finally separated to obtain flawless known good dies.
Accordingly, several known good dies are obtained through one test procedure, and the production yield may be enhanced.
However, the structure of the ceramic substrate 12 is complicated and limited to only one type of substrate, resulting in an increase in the manufacturing cost. Besides, the bonding pads 15 wire-bonded once are damaged, resulting in a decrease in their reliability.